Many circuit designs require fast resumption of operation after wakeup from sleep mode. In these designs, it is necessary to save the current data state before going into sleep mode and to restore the state at wakeup. One such on-chip retention method is the so-called dual pin balloon register, which uses separate save and restore control pins and a second slave latch for retention. This dual pin balloon register is illustrated in FIG. 1.
FIG. 1 is a high level block diagram of a prior art retention register 10. The retention register 10 is based on a conventional D-type flip-flop, which is represented by master-slave latches 12, 14. As will be familiar to those in this art, the Q output of the D flip-flop always takes on the state of the D input at the moment of a positive edge (or negative edge if the clock input is active low). It is called the D flip-flop for this reason, since the output takes the value of the D input or Data input, and delays it by one clock count. The retention register has an extra data preserving circuit sometimes referred to as a “shadow” latch or “balloon” latch 16. The latches 12, 14 of the D flip-flop are designed from standard, low Vt transistors whereas the balloon latch 16 is designed with weak high Vt transistors. This third latch 16 is connected to an always on power supply (True VDD) and holds the register state while the leaky master-slave register latches are powered down in sleep mode. This design requires complicated timing for transferring data back and forth between the balloon latches and the flip-flop on any transition from power-down to active mode and vice versa. The design complexities come in part from allowing the retention register to restore the retained data value regardless of the state of the clock. If the clock is low and the master latch is open and sampling input data the retained value is forced into the slave latch. If the clock is high, however, the retention latch value is forced into the master latch and then propagates to the slave latch when the clock goes low. The design also suffers from large size, power and delay related problems.
A lower power, small area retention flip-flop is desired.